1. Field of Invention
The present invention relates to a method of planarizing an inter-metal dielectric layer of a semiconductor device. More particularly, the present invention relates to a method of forming a planarized inter-metal dielectric layer that has a low dielectric constant (low k).
2. Description of Related Art
Recently, semiconductor manufacturing has advanced into the deep submicron process. Beside the miniaturization of semiconductor transistors so that operating speed of each device is increased, the deployment of innovative materials further boosts the performance and reliability of the devices.
In general, when the distance between neighboring metal lines in a semiconductor circuit is reduced, transmission of electrical signals through the metal lines is delayed. A phenomenon known as resistance-capacitance time delay (or RC time delay) is one of the factors that limit the operating speed of a device.
To reduce the RC time delay, a low resistance material is used to form the metal lines and low dielectric constant material is used to form the inter-metal dielectric layer.
However, low dielectric constant material typically comprises organic polymer. Thermal conductivity of the organic polymer is usually low. Thus, when the inter-metal dielectric layer is formed using the organic polymer, a reliability problem of metal lines may arise.